The present invention relates to the packaging of semiconductor devices in general and more specifically to a three-dimensional (3D) package and a method of forming the 3D package.
The number of transistors per square inch on integrated circuits (ICs) has been doubling approximately every eighteen (18) months in accordance with Moore's Law, making it possible to provide greater functionality with the same quantity of real estate. However, because the wiring capacity of printed circuit boards (PCBs) has not increased at a corresponding rate, system-level interconnect density is threatening to limit the added functionality attainable with the advances in IC technology.
To this end, 3D packaging has been developed to bridge the density differences between ICs and PCBs. 3D packaging involves either stacking two or more dies within a single package, or stacking and connecting completed packages. 3D packages offer significant size reductions compared to existing packages as they pack more silicon functions per square centimeter of board space and per cubic centimeter of application space. In light of these and numerous other advantages, 3D packages are capturing an increasing share of the market for IC packages. Thus, it would be desirable to have an inexpensive method of forming 3D packages having improved characteristics.
Accordingly, it is an object of the present invention to provide a 3D package having improved characteristics and an inexpensive method of fabricating such a package.